1. Field of the Invention
The present invention relates generally to a dynamic random access memory (DRAM). More particularly, the present invention relates to a DRAM using a modified silicon-on-insulator (SOI) technology in which transistors are formed by silicon direct bonding (SDB) following chemical-mechanical polishing (CMP) of a substrate surface, and after storage cell capacitors have been formed by silicon direct bonding and silicon-on-insulator technology. In addition, the present invention relates to a DRAM in which SOI devices are formed on only specific areas of the DRAM including the memory cells.
2. Description of the Prior Art
Remarkable progress has been made in the manufacture of ever more highly integrated DRAMS. For example, 4 Mbit DRAMs have now supplanted 1 Mbit DRAMs as the industry's standard memory device. Unfortunately, as conventional semiconductor memory devices shrink in size, it becomes increasingly difficult to obtain devices having memory cells of sufficient capacitance.
In conventional, highly integrated DRAMs, the predetermined capacitance of the cell storage capacitor must be kept relatively constant, in spite of the decreased surface area occupied by each of the cell. For example, in a 64 Mbit DRAM each storage cell is allocated an area of only 0.8 .mu.m.sup.2 to 1.0 .mu.m.sup.2.
In situations where the area allocated to each storage cell decreases to the point where cell capacitance becomes inadequate to hold the requisite charge, a soft error may occur upon exposure of the memory cell to .alpha. particles, thus creating reliability problems for the semiconductor memory device. Accordingly, the capacitance of storage cell capacitors must be kept relatively constant to avoid such errors, in spite of the necessary decrease in surface area allocated to individual storage cell capacitors.
In current conventional DRAMs having memory cells based on transistor-stacked capacitor combinations, one of a pair of storage capacitor electrodes is routinely formed with a three-dimensional structure. This three-dimensional structure increases cell capacitor capacitance by 30 to 40%, as compared with two-dimensional capacitor structures of similar size. Three-dimensional capacitor structures are but one example of recent efforts to increase memory cell capacitance without increasing the area allocated for each cell. Improved materials having high dielectric constants have also been studied. One proposed method for obtaining higher cell capacitance in defined small areas is described in "A 1.28 .mu.m Bit-Line Shielded Memory Cell Technology for 64 MB DRAMS" among the 1990 symposium of VLSI TECHNOLOGY.
Conventional CMOS memory devices suffer from a plurality of design and performance problems. Among these, current fabrication processes and resulting structures may inadvertently create active parasitic devices within the memory device structure, such as parasitic metal oxide semiconductor transistors, or parasitic bipolar transistors in a PN junction-separation structure. In addition, common problems include the deterioration of electrical devices within the memory device, and the occurrence of soft errors due to the latch-up phenomenon. In order to prevent these problems while attaining higher integration densities, silicon-on-insulator (SOI) techniques have been studied wherein insulating layers are formed as sidewalls of an insulating substrate formed of a material such as SiC.sub.2, and wherein silicon single crystalline wells are formed in these insulating layers to form semiconductor devices.
These techniques have advantages of perfect isolation of electrical elements, and high speed performance free from latch-up and soft errors. Other advantages include the ability to determine the width of insulating layers for isolation based upon photo-etching process steps, etc. Finally, increased integration based on the micro-miniaturization can be obtained in an environment which allows the application with three-dimensional devices.
According to the above techniques, a semiconductor device having a SOI structure is formed by forming an amorphous or polysilicon layer on an amorphous insulating substrate such as SiO.sub.2 and by performing recrystallization on the polysilicon layer. Separation by implanted oxygen (SIMOX) processes and full isolation by porous oxidized silicon (FIPOS) processes are also known as another approach.
However, these techniques are not without their drawbacks. When it comes to SIMOX technologies, a specially designed oxide ion implanting means is required to form an insulating layer inside the substrate. The FIPOS processes require anodization for just these processes. Zone melting (ZMR) requires recrystallization.
A method of forming a conventional DRAM is now described with reference to FIG. 1. In FIG. 1, a field oxide layer 2 is formed by a selective oxidation on a silicon substrate 1 and isolation of electrical elements is performed. After that, a gate oxide 8 is grown, and a gate electrode 17 is patterned to form a source/drain region. Inter layer insulation is carried out by an oxide layer 19 formed by a chemical vapor deposition method. Next, a conductive layer 21 is deposited and patterned.
After a second interlayer insulation is carried out, a contact hole is opened so that a lower capacitor electrode 7 contacts the substrate. Thereafter, lower electrode 7 is patterned. A dielectric layer 10 and an upper electrode 9 are then formed.
Successively, after a third interlayer insulation is performed, a protective layer 25 is finally formed to complete the manufacture of the semiconductor memory cell.
As shown in the above process, a memory cell having sufficient capacitance is attained in the manufacture of the highly integrated DRAM by use of a three-dimensional stack type capacitor. Unfortunately, in stack type capacitor applications greater than 64 Meg, the storage cell obtains a very high profile in order to secure the capacitance required by the cell capacitor. If the storage cell (or node) is raised in this manner, the large step-like difference between cell part and a peripheral part, contact or metallization can not be easily performed.
In the formation of P-MOS transistors, high temperature processing should be minimized in order to maintain transistor characteristics and the isolation of electrical elements. As a result, it is hard to perform planarization by borophosphosilicate glass (BPSG) flow due to this condition.
Increased DRAM integration brings with it increased difficulty in forming patterns. That is, not only is the size of patterns small, but also high overlay accuracy is necessary.
Since there is a large step-like difference resulting from the height of the cell capacitor, it is difficult to secure a sufficient alignment margin.
If device planarity is increased so as to remove the step-like difference, the depth of the contact metallization must be increased. Various problems may occur by step-coverage or etch damage. One study tried to solve these problems by forming a capacitor in advance by direct wafer bonding and silicon-on-insulator processes and then making transistors on the opposite silicon surface. However, if a DRAM cell is made this way, peripheral circuit devices become SOI devices, and it is difficult to find a processing condition that meets both characteristics.
That is to say, n-type MOS and p-type MOS transistors having different widths and lengths should preferably be made into SOI devices, but heretofore it has been difficult to form active devices of different size using a SOI technique.